Jorge Semião
Orcid: 0000-0002-7667-7910
According to our database1,
Jorge Semião
authored at least 45 papers
between 1999 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on w3.ualg.pt
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Bibliography
2022
Quasi-Resonant DC-DC Converter Single-Switch for Single-Input Bipolar-Output Applications.
Proceedings of the IECON 2022, 2022
Proceedings of the Universal Access in Human-Computer Interaction. Novel Design Approaches and Technologies, 2022
2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2020
Proceedings of the Convergence of Artificial Intelligence and the Internet of Things, 2020
2019
Proceedings of the IECON 2019, 2019
2018
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018
Development of an Energy Management System for the Charge Scheduling of Plug-in Electric Vehicles.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018
2015
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Integration of a Food Distribution Routing Optimization Software with an Enterprise Resource Planner.
Proceedings of the GISTAM 2015, 2015
Integration of a Real-Time Stochastic Routing Optimization Software with an Enterprise Resource Planner.
Proceedings of the Geographical Information Systems Theory, Applications and Management, 2015
2014
Proceedings of the 2014 IEEE International Conference on Smart Grid Communications, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
J. Electron. Test., 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.
J. Electron. Test., 2012
IEEE Des. Test Comput., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.
J. Low Power Electron., 2011
Lower <i>V</i><sub>DD</sub> Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.
J. Low Power Electron., 2011
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects.
Proceedings of the 12th Latin American Test Workshop, 2011
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications.
Proceedings of the 12th Latin American Test Workshop, 2011
Modeling the effect of process variations on the timing response of nanometer digital circuits.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
2010
J. Low Power Electron., 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
2009
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
Proceedings of the 10th Latin American Test Workshop, 2009
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
J. Low Power Electron., 2008
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.
J. Low Power Electron., 2008
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
1999
Proceedings of the 4th European Test Workshop, 1999