Jorge Juan

According to our database, Jorge Juan authored at least 6 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of seven.
• Erdős number of six.

2012

Network Time Synchronization: A Full Hardware Approach.

Jorge Juan, Julian Viejo, Manuel J. Bellido

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2010

Design and implementation of a suitable core for on-chip long-term verification.

Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa

Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

2009

Efficient techniques and methodologies for embedded system design usign free hardware and open standards.

Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.

Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Design of a FFT/IFFT module as an IP core suitable for embedded systems.

Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz

Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2006

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.

Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos

Proceedings of the International Symposium on Industrial Embedded Systems, 2006