Jorge Echavarria

Orcid: 0000-0002-3751-5273

According to our database1, Jorge Echavarria authored at least 21 papers between 2014 and 2024.

Collaborative distances:

Timeline

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2024
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Bibliography

2024
A Software Platform to Support Disaggregated Quantum Accelerators.
Proceedings of the SC24-W: Workshops of the International Conference for High Performance Computing, 2024

QDMI - Quantum Device Management Interface: Hardware-Software Interface for the Munich Quantum Software Stack.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

Achieving Pareto-Optimality in Quantum Circuit Compilation via a Multi-Objective Heuristic Optimization Approach.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

QPI: A Programming Interface for Quantum Computers.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

From the Physics Lab to the Computer Lab: Towards Flexible and Comprehensive DevOps for Quantum Computing.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2022
On the Approximation of Arithmetic Functions and Logic Synthesis of Approximate Very Large Boolean Networks.
PhD thesis, 2022

Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains.
it Inf. Technol., 2022

2021
IP-cores watermarking scheme at behavioral level using genetic algorithms.
Eng. Appl. Artif. Intell., 2021

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains.
CoRR, 2021

Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.
Proceedings of the 26th IEEE European Test Symposium, 2021

Approximate Logic Synthesis of Very Large Boolean Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Probabilistic Error Propagation through Approximated Boolean Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders.
IEEE Embed. Syst. Lett., 2018

Can Approximate Computing Reduce Power Consumption on FPGAs?
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design space exploration of multi-output logic function approximations.
Proceedings of the International Conference on Computer-Aided Design, 2018

AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

2016
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A LUT-Based Approximate Adder.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2014
FSM merging and reduction for IP cores watermarking using Genetic Algorithms.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014


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