Jörg Brakensiek
According to our database1,
Jörg Brakensiek
authored at least 15 papers
between 2001 and 2011.
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Bibliography
2011
2010
Proceedings of 2nd International Conference on Automotive User Interfaces and Interactive Vehicular Applications, 2010
2009
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009
2008
OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis.
J. Syst. Archit., 2008
Proceedings of the 1st Workshop on Isolation and Integration in Embedded Systems, 2008
2007
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures.
J. Syst. Archit., 2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
2006
Proceedings of the Embedded Computer Systems: Architectures, 2006
Proceedings of the 14th European Signal Processing Conference, 2006
2004
Dynamic power optimization of the trace-back process for the Viterbi algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Proceedings of the 13th IEEE International Symposium on Personal, 2002
2001
Constant modulus algorithm for blind equalization of multipath transmitted video signals in cable networks.
Signal Process. Image Commun., 2001