Jörg Bormann
According to our database1,
Jörg Bormann
authored at least 21 papers
between 1992 and 2023.
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Bibliography
2023
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
IEEE Trans. Computers, 2023
2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
IPSJ Trans. Syst. LSI Des. Methodol., 2013
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013
A Hardware-Dependent Model for SAT-based Verification of Interrupt-Driven Low-level Embedded System Software.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Compositional Completeness over reactive Constraints.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
A computational model for SAT-based verification of hardware-dependent low-level embedded system software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
2010
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010
Analyzing <i>k</i>-step induction to compute invariants for SAT-based property checking.
Proceedings of the 47th Design Automation Conference, 2010
2009
Proceedings of the Forum on specification and Design Languages, 2009
2008
Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking.
Theor. Comput. Sci., 2008
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
2004
Formale Verifikation eines Sonet/SDH Framers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Semi-formal Verification of the quasi-static behavior of Mixed-Signal Circuits by SAT-based Property Checking.
Proceedings of the International Symposium on Leveraging Applications of Formal Methods, 2004
2001
Informationstechnik Tech. Inform., 2001
Formale Verifikation wird zum Handwerk.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
1995
Proceedings of the 32st Conference on Design Automation, 1995
1992
Invited Talk: Formal Design in an Industrial Research Laboratory: Lessons and Perspectives.
Proceedings of the Designing Correct Circuits, 1992