Jörg Biesenack

According to our database, Jörg Biesenack authored at least 5 papers between 1991 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1994

Scheduling of behavioral VHDL by retiming techniques.

Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

The Siemens high-level synthesis system CALLAS.

Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy

IEEE Trans. Very Large Scale Integr. Syst., 1993

1992

Data Part Optimizations in the CALLAS Synthesis Environment.

Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer

Proceedings of the Synthesis for Control Dominated Circuits, 1992

Flexible timing specification in a VHDL synthesis subset.

A. Stoll, Jörg Biesenack, Steffen Rumler

Proceedings of the conference on European design automation, 1992

1991

A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment.

Norbert Wehn, Jörg Biesenack, Michael Pilsl

Proceedings of the VLSI 91, 1991