Jörg Berthold

According to our database, Jörg Berthold authored at least 19 papers between 1997 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Degradation and recovery of variability due to BTI.

Christian Schlünder, Jörg Berthold, Fabian Proebster, Andreas Martin, Wolfgang Gustin, Hans Reisinger

Microelectron. Reliab., 2016

2011

Architecture and implementation of a Software-Defined Radio baseband processor.

Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Low power design of the X-GOLD^® SDR 20 baseband processor.

Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth

Proceedings of the Design, Automation and Test in Europe, 2010

2007

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.

Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer

IEEE J. Solid State Circuits, 2007

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.

Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel

IEEE J. Solid State Circuits, 2007

Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits.

Christian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement.

Thomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.

Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel

IEEE J. Solid State Circuits, 2006

Circuit design issues in multi-gate FET CMOS technologies.

Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.

Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits.

Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha

IEEE J. Solid State Circuits, 2005

Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.

Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.

Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel

Proceedings of the Integrated Circuit and System Design, 2004

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.

Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel

Proceedings of the Integrated Circuit and System Design, 2004

2003

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.

Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.

Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos

Proceedings of the IFIP VLSI-SoC 2003, 2003

Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.

Tim Schoenauer, Jörg Berthold, Christoph Heer

Proceedings of the Integrated Circuit and System Design, 2003

An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment.

Ettore Amirante, Jürgen Fischer, Markus Lang, Agnese Bargagli-Stoffi, Jörg Berthold, Christoph Heer, Doris Schmitt-Landsiedel

Proceedings of the ESSCIRC 2003, 2003

1997

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.

M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf

IEEE Trans. Very Large Scale Integr. Syst., 1997