Joonsung Kim

Orcid: 0000-0002-5432-7813

Affiliations:
  • Seoul National University, Korea


According to our database1, Joonsung Kim authored at least 18 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
GCStack: A GPU Cycle Accounting Mechanism for Providing Accurate Insight Into GPU Performance.
IEEE Comput. Archit. Lett., 2024

2023
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks.
ACM Trans. Archit. Code Optim., March, 2023

2022
LSim: Fine-Grained Simulation Framework for Large-Scale Performance Evaluation.
IEEE Comput. Archit. Lett., 2022

3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Performance Modeling and Practical Use Cases for Black-Box SSDs.
ACM Trans. Storage, 2021

Symbol Level Beam Selection and Precoding in mm-wave Beamspace MU-MISO Systems.
Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021

UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP Models.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2019
FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MnnFast: a fast and scalable system architecture for memory-augmented neural networks.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

CIDR: A Cost-Effective In-Line Data Reduction System for Terabit-Per-Second Scale SSD Arrays.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

μLayer: Low Latency On-Device Inference Using Cooperative Single-Layer Acceleration and Processor-Friendly Quantization.
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

Enforcing Last-Level Cache Partitioning through Memory Virtual Channels.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
SSD Performance Modeling Using Bottleneck Analysis.
IEEE Comput. Archit. Lett., 2018

A Scalable HW-Based Inline Deduplication for SSD Arrays.
IEEE Comput. Archit. Lett., 2018

DynaMix: Dynamic Mobile Device Integration for Efficient Cross-device Resource Sharing.
Proceedings of the 2018 USENIX Annual Technical Conference, 2018

SSDcheck: Timely and Accurate Prediction of Irregular Behaviors in Black-Box SSDs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2016
CloudSwap: A Cloud-Assisted Swap Mechanism for Mobile Devices.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016


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