Joonho Kong

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

2023

Linearization Weight Compression and In-Situ Hardware-Based Decompression for Attention-Based Neural Machine Translation.

[BibT_eX]

[DOI]

Mijin Go

IEEE Access, 2023

AMBITION: Ambient Temperature Aware VM Allocation for Edge Data Centers.

[BibT_eX]

[DOI]

IEEE Access, 2023

2022

Sparse convolutional neural network acceleration with lossless input feature map compression for resource-constrained systems.

[BibT_eX]

[DOI]

Jisu Kwon

IET Comput. Digit. Tech., 2022

Security Issues in Situational Awareness: Adversarial Threats and Mitigation Techniques.

[BibT_eX]

[DOI]

IEEE Secur. Priv., 2022

Row-Wise Product-Based Sparse Matrix Multiplication Hardware Accelerator With Optimal Load Balancing.

[BibT_eX]

[DOI]

IEEE Access, 2022

2021

Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

FogSurv: A Fog-Assisted Architecture for Urban Surveillance Using Artificial Intelligence and Data Fusion.

[BibT_eX]

[DOI]

IEEE Access, 2021

Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors.

[BibT_eX]

[DOI]

IEEE Access, 2021

Arithmetic Coding-Based 5-Bit Weight Encoding and Hardware Decoder for CNN Inference in Edge Devices.

[BibT_eX]

[DOI]

Jong Hun Lee

IEEE Access, 2021

2020

An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Near-Threshold L1 Data Cache for Yield Management Under Process Variations.

[BibT_eX]

[DOI]

Jae Young Hur

IEEE Access, 2020

CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge.

[BibT_eX]

[DOI]

Yeongmin Kim

IEEE Access, 2020

Page Table Compaction for TLB Coalescing.

[BibT_eX]

[DOI]

Jae Young Hur

IEEE Access, 2020

An Integrated Safe and Secure Approach for Authentication and Secret Key Establishment in Automotive Cyber-Physical Systems.

[BibT_eX]

[DOI]

Naresh Kumar Giri

Proceedings of the Intelligent Computing, 2020

2019

Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

A Framework for Distributed Deep Neural Network Training with Heterogeneous Computing Platforms.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

2018

A Survey on Recent OS-Level Energy Management Techniques for Mobile Processing Units.

[BibT_eX]

[DOI]

Young Geun Kim

IEEE Trans. Parallel Distributed Syst., 2018

3D die-stacked DRAM thermal management via task allocation and core pipeline control.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

CT-Cache: Compressed Tag-Driven Cache Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

An efficient trade-off between yield and energy for eDRAM caches under process variations.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs.

[BibT_eX]

[DOI]

Kwangho Lee

IEICE Electron. Express, 2017

Architecting large-scale SRAM arrays with monolithic 3D integration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016

A novel technique for technology-scalable STT-RAM based L1 instruction cache.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

2015

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core Processors.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2014

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs.

[BibT_eX]

[DOI]

Praveen Kumar Pendyala

Ahmad-Reza Sadeghi

Christian Wachsmann

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Low-power resource binding by postsilicon customization.

[BibT_eX]

[DOI]

Mehrdad Majzoobi

ACM Trans. Design Autom. Electr. Syst., 2013

Process variation-tolerant 3D microprocessor design: An efficient architectural solution.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012

Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Enhancing online power estimation accuracy for smartphones.

[BibT_eX]

[DOI]

Minyong Kim

IEEE Trans. Consumer Electron., 2012

Recent thermal management techniques for microprocessors.

[BibT_eX]

[DOI]

Kevin Skadron

ACM Comput. Surv., 2012

An online power estimation technique for multi-core smartphones with advanced display components.

[BibT_eX]

[DOI]

Minyong Kim

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

Exploiting narrow-width values for process variation-tolerant 3-D microprocessors.

[BibT_eX]

[DOI]