Joong Sik Kih
According to our database1,
Joong Sik Kih
authored at least 3 papers
between 2006 and 2011.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006