Joon-Sung Yang

According to our database, Joon-Sung Yang authored at least 85 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network Accelerators.

Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang

IEEE Trans. Computers, September, 2024

Survey and Evaluation of Converging Architecture in LLMs based on Footsteps of Operations.

Seongho Kim, Jihyun Moon, Juntaek Oh, Insu Choi, Joon-Sung Yang

CoRR, 2024

LOCo: LPDDR Optimization with Compression and IECC scheme for DNN Inference.

Jae-Youn Hong, Sungkyu Kim, Je-Woo Jang, Joon-Sung Yang

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm.

Dongjin Shin, Insu Choi, Joon-Sung Yang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

A convertible neural processor supporting adaptive quantization for real-time neural networks.

Hongju Kal, Hyoseong Choi, Ipoom Jeong, Joon-Sung Yang, Won Woo Ro

J. Syst. Archit., December, 2023

CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks.

Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

EUNNet: Efficient UN-Normalized Convolution Layer for Stable Training of Deep Residual Networks Without Batch Normalization Layer.

Khanh-Binh Nguyen, Jaehyuk Choi, Joon-Sung Yang

IEEE Access, 2023

Boosting Semi-Supervised Learning by bridging high and low-confidence predictions.

Khanh-Binh Nguyen, Joon-Sung Yang

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

VSCHH 2023: A Benchmark for the View Synthesis Challenge of Human Heads.

Youngkyoon Jang, Jiali Zheng, Jifei Song, Helisa Dhamo, Eduardo Pérez-Pellitero, Thomas Tanay, Matteo Maggioni, Richard Shaw, Sibi Catley-Chandar, Yiren Zhou, Jiankang Deng, Ruijie Zhu, Jiahao Chang, Ziyang Song, Jiahuan Yu, Tianzhu Zhang, Khanh-Binh Nguyen, Joon-Sung Yang, Andreea Dogaru, Bernhard Egger, Heng Yu, Aarush Gupta, Joel Julin, László A. Jeni, Hyeseong Kim, Jungbin Cho, Dosik Hwang, Deukhee Lee, Doyeon Kim, Dongseong Seo, SeungJin Jeon, YoungDon Choi, Jun Seok Kang, Ahmet Cagatay Seker, Sang Chul Ahn, Ales Leonardis, Stefanos Zafeiriou

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator.

Je-Woo Jang, Thai-Hoang Nguyen, Joon-Sung Yang

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table.

JaeHwa Jeon, Jae-Youn Hong, Sunghoon Kim, Insu Choi, Joon-Sung Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Networks.

Insu Choi, Jae-Youn Hong, JaeHwa Jeon, Joon-Sung Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change Memory.

Muhammad Imran, Taehyun Kwon, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM.

Muhammad Imran, Taehyun Kwon, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Computers, 2022

Checkerboard Dropout: A Structured Dropout With Checkerboard Pattern for Convolutional Neural Networks.

Khanh-Binh Nguyen, Jaehyuk Choi, Joon-Sung Yang

IEEE Access, 2022

DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks.

Thai-Hoang Nguyen, Muhammad Imran, Joon-Sung Yang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural Network.

Seo-Seok Lee, Joon-Sung Yang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Bipolar vector classifier for fault-tolerant deep neural networks.

Suyong Lee, Insu Choi, Joon-Sung Yang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency.

Taehyun Kwon, Muhammad Imran, Joon-Sung Yang

IEEE Trans. Computers, 2021

Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks.

Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs.

Inayat Ullah, Joon-Sung Yang, Jaeyong Chung

IEEE Trans. Very Large Scale Integr. Syst., 2020

Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization.

Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang

IEEE Trans. Very Large Scale Integr. Syst., 2020

Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement.

Taehyun Kwon, Muhammad Imran, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction.

Taehyun Kwon, Muhammad Imran, Joon-Sung Yang

IEEE Access, 2020

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits.

Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang

IEEE Access, 2020

Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture.

Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM.

Muhammad Imran, Taehyun Kwon, Joon-Sung Yang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Factored Radix-8 Systolic Array for Tensor Processing.

Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code.

Sangmok Jeong, SeungYup Kang, Joon-Sung Yang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems.

Yongshin Kang, Joon-Sung Yang, Jaeyong Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems.

Jaeyong Chung, Taehwan Shin, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density.

Muhammad Imran, Taehyun Kwon, Jung Min You, Joon-Sung Yang

Proceedings of the International Conference on Computer-Aided Design, 2019

MRLoc: Mitigating Row-hammering based on memory Locality.

Jung Min You, Joon-Sung Yang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis.

Jae-San Kim, Joon-Sung Yang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Computation Offloading of Acoustic Model for Client-Edge-Based Speech-Recognition.

Young-Min Lee, Joon-Sung Yang

Proceedings of the 2019 International Conference on Compliers, 2019

2018

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint.

Taehee Lee, David Z. Pan, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning.

Sae-Eun Kim, Jaeyong Chung, Joon-Sung Yang

IEEE Trans. Computers, 2018

READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution.

Hyunseung Han, Jaeyong Chung, Joon-Sung Yang

IEEE Trans. Computers, 2018

New library development method by FSM based cell pattern extraction.

Byung-Su Kim, Tae Hee Han, Joon-Sung Yang, Jaeyong Chung

IEICE Electron. Express, 2018

Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement.

Taehyun Kwon, Muhammad Imran, Jung Min You, Joon-Sung Yang

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring.

Byung-Su Kim, Joon-Sung Yang

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system.

Seonbong Kim, Joon-Sung Yang

Proceedings of the 55th Annual Design Automation Conference, 2018

Test cost reduction for <i>X</i>-value elimination by scan slice correlation analysis.

Hyunsu Chae, Joon-Sung Yang

Proceedings of the 55th Annual Design Automation Conference, 2018

System level performance analysis and optimization for the adaptive clocking based multi-core processor.

Byung-Su Kim, Joon-Sung Yang

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction.

Chang-Hyun Oh, Sae-Eun Kim, Joon-Sung Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios.

Taehee Lee, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC.

Hyunseung Han, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Physical-aware gating element insertion for thermal-safe scan shift operation.

Taehee Lee, Joon-Sung Yang

IEICE Electron. Express, 2017

Non-linear library characterization method for FinFET logic cells by L1-minimization.

Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

PUFSec: Device fingerprint-based security architecture for Internet of Things.

So-Yeon Park, Sunil Lim, Dahee Jeong, Jungjin Lee, Joon-Sung Yang, HyungJune Lee

Proceedings of the 2017 IEEE Conference on Computer Communications, 2017

MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability.

Seung-Yeob Lee, Joon-Sung Yang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress.

Seonbong Kim, Joon-Sung Yang

Proceedings of the 2017 International Conference on Compilers, 2017

2016

Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation.

Joon-Sung Yang, Jinsuk Chung, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Temperature and voltage droop-aware test scheduling during scan shift operation.

Taehee Lee, YongJoon Kim, Joon-Sung Yang

IEICE Electron. Express, 2016

Subthreshold 8T SRAM sizing utilizing short-channel V_t roll-off and inverse narrow-width effect.

Ik Joon Chang, Joon-Sung Yang

IEICE Electron. Express, 2016

Memory ECC architecutre utilizing memory column spares.

Jong Hyuk Park, Joon-Sung Yang

Proceedings of the International SoC Design Conference, 2016

eFuse based IC authentication architecture.

Seung-Yeob Lee, Joon-Sung Yang

Proceedings of the International SoC Design Conference, 2016

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint.

Taehee Lee, JongWon Yi, Joon-Sung Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments.

Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning.

Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang

Proceedings of the 53rd Annual Design Automation Conference, 2016

A BIRA using fault-free memory region for area reduction.

Chang-Hyun Oh, Sae-Eun Kim, Joon-Sung Yang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

System-level failure simulation and memory allocation scheme in 3D memory.

Jung-Jin Lee, Joon-Sung Yang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Devil in a box: Installing backdoors in electronic door locks.

Seongyeol Oh, Joon-Sung Yang, Andrea Bianchi, Hyoungshick Kim

Proceedings of the 13th Annual Conference on Privacy, Security and Trust, 2015

Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield.

Byung-Jun Jang, Chan-Ho Lee, Sung-Hun Sim, Kyu-Won Choi, Do-Hun Byun, Yeon-Ho Jung, Ki-Man Park, Dong-Yeon Heo, Gyu-Hong Kim, Joon-Sung Yang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Asymmetric ECC organization in 3D-memory via spare column utilization.

Hyunseung Han, Joon-Sung Yang

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression.

Joon-Sung Yang, Jinkyu Lee, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations.

Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Communication-aware custom topology generation for VFI network-on-chip.

Chang Lin Li, Jae Hoon Lee, Joon-Sung Yang, Tae Hee Han

IEICE Electron. Express, 2014

Low-power shared memory architecture power mode for mobile system-on-chip.

Junghwa Kim, Jun-Ho Huh, Soo-Yong Kim, Suk Won Kim, Joon-Sung Yang

IEICE Electron. Express, 2014

2013

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2013

Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion.

Joon-Sung Yang, Ik Joon Chang

IEICE Trans. Electron., 2013

Enhanced algorithm of combining trace and scan signals in post-silicon validation.

Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Dynamic Trace Signal Selection for Post-Silicon Validation.

Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

X-Canceling MISR Architectures for Output Response Compaction With Unknown Values.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.

Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie

IEEE Trans. Computers, 2012

Bit-error rate improvement of TLC NAND Flash using state re-ordering.

Ik Joon Chang, Joon-Sung Yang

IEICE Electron. Express, 2012

2011

Efficient Function Mapping in Nanoscale Crossbar Architecture.

Joon-Sung Yang, Rudrajit Datta

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2009

Automated Selection of Signals to Observe for Efficient Silicon Debug.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

An industrial case study for X-canceling MISR.

Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak

Proceedings of the 2009 IEEE International Test Conference, 2009

Test point insertion using functional flip-flops to drive control points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Enhancing Silicon Debug via Periodic Monitoring.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.

Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007