Joohwan Cho
According to our database1,
Joohwan Cho
authored at least 11 papers
between 2014 and 2024.
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Bibliography
2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.
IEEE J. Solid State Circuits, 2023
A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2018
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2015
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques.
IEEE J. Solid State Circuits, 2015
2014
A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014