Jooheung Lee

J. Signal Process. Syst., January, 2024

2017

Write-Amount-Aware Management Policies for STT-RAM Caches.

[BibT_eX]

[DOI]

Hyeonggyu Kim

Soontae Kim

IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy efficient processing of motion estimation for embedded multimedia systems.

[BibT_eX]

[DOI]

Multim. Tools Appl., 2017

Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC.

[BibT_eX]

[DOI]

Iljung Yoon

Anand Paul

Intell. Autom. Soft Comput., 2017

2016

Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences.

[BibT_eX]

[DOI]

Iljung Yoon

Heewon Joung

J. Sensors, 2016

2015

Activity-Based Resource Allocation for Motion Estimation Engines.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2015

2014

Self-Adapting Resource Escalation for Resilient Signal Processing Architectures.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2014

2013

Fault Demotion Using Reconfigurable Slack (FaDReS).

[BibT_eX]

[DOI]

Naveed Imran

Ronald F. DeMara

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration.

[BibT_eX]

[DOI]

Rakan Khraisha

J. Signal Process. Syst., 2012

Error surface-aware modeling algorithm for quarter-pixel motion estimation.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2012

2011

Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

2010

A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Rakan Khraisha

Proceedings of the IEEE International Conference on Acoustics, 2010

Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors.

[BibT_eX]

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2009

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2009

Efficient VLSI architecture for video transcoding.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2009

A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration.

[BibT_eX]

Sumedha Gupta Kodipyaka

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008

Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study.

[BibT_eX]

Yidong Liu

Srinivasan Santhanam

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.

[BibT_eX]

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field.

[BibT_eX]

Hao Li

Proceedings of the 2008 International Conference on Security & Management, 2008

2006

Block-based frequency scalable technique for efficient hierarchical coding.

[BibT_eX]

[DOI]

Rajarathnam Chandramouli

IEEE Trans. Signal Process., 2006

An efficient architecture for motion estimation and compensation in the transform domain.

[BibT_eX]

[DOI]

Wayne H. Wolf

IEEE Trans. Circuits Syst. Video Technol., 2006

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2006

2005

High Performance Array Processor for Video Decoding.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004

An Architecture for Motion Estimation in the Transform Domain.

[BibT_eX]

[DOI]

Wayne H. Wolf

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Efficient VLSI implementation of inverse discrete cosine transform [image coding applications].

[BibT_eX]

[DOI]