Jooeun Bang
Orcid: 0000-0001-9074-617X
According to our database1,
Jooeun Bang
authored at least 6 papers
between 2018 and 2023.
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Bibliography
2023
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop.
IEEE J. Solid State Circuits, 2022
2021
A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018