Joo-Hwan Cho
According to our database1,
Joo-Hwan Cho
authored at least 6 papers
between 2002 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2010
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2007
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.
IEEE J. Solid State Circuits, 2007
2002
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM.
IEEE J. Solid State Circuits, 2002