Jonne Poikonen

According to our database1, Jonne Poikonen authored at least 32 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2019
Embedded processing methods for online visual analysis of laser welding.
J. Real Time Image Process., 2019

Solid-State Memcapacitors and Their Applications.
Proceedings of the Handbook of Memristor Networks., 2019

2018
An Efficient Multi-sensor Fusion Approach for Object Detection in Maritime Environments.
Proceedings of the 21st International Conference on Intelligent Transportation Systems, 2018

Object Detection Based on Multi-sensor Proposal Fusion in Maritime Environment.
Proceedings of the 17th IEEE International Conference on Machine Learning and Applications, 2018

2017
Fast thermopile readout circuit arrangement for array processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
Online seam tracking for laser welding with a vision chip and FPGA enabled camera system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 512×512-cell associative CAM/Willshaw memory with vector arithmetic.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Memristive Circuits for LDPC Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Seam tracking with adaptive image capture for fine-tuning of a high power laser welding process.
Proceedings of the Seventh International Conference on Machine Vision, 2014

2013
Characterizing Spatters in Laser Welding of Thick Steel Using Motion Flow Analysis.
Proceedings of the Image Analysis, 18th Scandinavian Conference, 2013

2010
Rate-distortion performance analysis of an analog motion estimation array.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
An 8times 8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-muhboxm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation.
EURASIP J. Adv. Signal Process., 2009

Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Temperature Compensation in Combination Selection based Mismatch Calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Live Demonstration: MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Locally adaptive image sensing with the 64x64 cell MIPA4k mixed-mode image processor array.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Space-dependent binary image processing within a 64x64 mixed-mode array processor.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A ring-oscillator-based active quenching and active recharge circuit for single photon avalanche diodes.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Centroiding and classification of objects using a processor array with a scalable region of interest.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A 12-bit Current-Steering DAC with Calibration by Combination Selection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
On the topographic equivalence between voltage mode and current mode ranked order filters for array processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Current source calibration by combination selection of minimum sized devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A Gray-coded digital-to-analog converter for a mixed-mode processor array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Rank identification for an analog ranked order filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Effect of mismatch on a ranked-order extractor array [image processing applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A ranked order filter implementation for parallel analog processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A gray-code current-mode ADC for mixed-mode cellular computer.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Realization of an analog current-mode 2D DCT.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An area-efficient full-wave current rectifier for analog array processing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 32×32 cellular test chip targeting new functionalities.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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