Jongwook Kye
According to our database1,
Jongwook Kye
authored at least 9 papers
between 2012 and 2022.
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Bibliography
2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm<sup>2</sup> at 0.85V.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 14.7Mb/mm<sup>2</sup> 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2016
Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
2012
Impact of lithography retargeting process on low level interconnect in 20nm technology.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Lithography and design integration - New paradigm for the technology architecture development.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012