Jongwha Kim
Orcid: 0009-0001-1636-3952
According to our database1,
Jongwha Kim
authored at least 3 papers
between 2023 and 2025.
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Bibliography
2025
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces.
IEEE J. Solid State Circuits, February, 2025
2023
The Return of the King: The Importance of Killer Content in a Competitive OTT Market.
J. Theor. Appl. Electron. Commer. Res., 2023
A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25<sup>%</sup>-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023