Jongsun Kim
Orcid: 0000-0002-9611-0268
According to our database1,
Jongsun Kim
authored at least 43 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
Microelectron. J., 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
2022
IEEE Access, 2022
A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication.
IEICE Electron. Express, 2020
Circuits Syst. Signal Process., 2020
Development of Artificial Neural Network System to Recommend Process Conditions of Injection Molding for Various Geometries.
Adv. Intell. Syst., 2020
Proceedings of the International SoC Design Conference, 2020
2019
A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links.
IEICE Electron. Express, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
2018
A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs.
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEICE Electron. Express, 2017
IEICE Electron. Express, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2012
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling.
IEEE J. Solid State Circuits, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
2011
A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects.
IEICE Trans. Electron., 2011
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEICE Electron. Express, 2010
2009
Area-efficient digitally controlled CMOS feedback delay element with programmable duty cycle.
IEICE Electron. Express, 2009
2008
IEEE Trans. Computers, 2008
2007
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the Advances in Biometrics, International Conference, 2007
A Changeable Biometric System That Uses Parts-Based Localized Representation for Face Recognition.
Proceedings of the 2007 IEEE Workshop on Automatic Identification Advanced Technologies, 2007
2005
Effective Representation Using ICA for Face Recognition Robust to Local Distortion and Partial Occlusion.
IEEE Trans. Pattern Anal. Mach. Intell., 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the Image Analysis and Processing, 2005
2004
Proceedings of the Biometric Authentication, First International Conference, 2004
Proceedings of the Biometric Authentication, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Proceedings of the Computer and Information Sciences, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the Biometric Authentication, 2002