JongRyun Choi

According to our database, JongRyun Choi authored at least 5 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.

Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2017

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.

Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology.

Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2012

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.

Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2010

Process variation tolerant all-digital multiphase DLL for DDR3 interface.

Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010