Jongman Kim

Orcid: 0000-0003-2053-8994

According to our database1, Jongman Kim authored at least 46 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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On csauthors.net:

Bibliography

2024
Machine Learning Based Abnormal Gait Classification with IMU Considering Joint Impairment.
Sensors, September, 2024

2023
Quantification of Comfort for the Development of Binding Parts in a Standing Rehabilitation Robot.
Sensors, February, 2023

2022
Fall-from-Height Detection Using Deep Learning Based on IMU Sensor Data for Accident Prevention at Construction Sites.
Sensors, 2022

sEMG-Based Hand Posture Recognition and Visual Feedback Training for the Forearm Amputee.
Sensors, 2022

2021
The Performance of Post-Fall Detection Using the Cross-Dataset: Feature Vectors, Classifiers and Processing Conditions.
Sensors, 2021

sEMG-Based Hand Posture Recognition Considering Electrode Shift, Feature Vectors, and Posture Groups.
Sensors, 2021

2020
Detection of Pre-Impact Falls from Heights Using an Inertial Measurement Unit Sensor.
Sensors, 2020

Enhanced Algorithm for the Detection of Preimpact Fall for Wearable Airbags.
Sensors, 2020

2019
Evaluation of Inertial Sensor-Based Pre-Impact Fall Detection Algorithms Using Public Dataset.
Sensors, 2019

2017
HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs.
ACM Trans. Design Autom. Electr. Syst., 2017

2015
Size-Aware Cache Management for Compressed Cache Architectures.
IEEE Trans. Computers, 2015

Synchronous I/O Scheduling of Independent Write Caches for an Array of SSDs.
IEEE Comput. Archit. Lett., 2015

Subtleties of Run-Time VirtualAddress Stacks.
IEEE Comput. Archit. Lett., 2015

2014
Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression.
ACM Trans. Design Autom. Electr. Syst., 2014

Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion.
Des. Autom. Embed. Syst., 2014

Balancing context switch penalty and response time with elastic time slicing.
Proceedings of the 21st International Conference on High Performance Computing, 2014

2013
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Preemptible I/O Scheduling of Garbage Collection for Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era.
ACM Trans. Archit. Code Optim., 2013

Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing.
Parallel Comput., 2013

Do we need wide flits in Networks-on-Chip?
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Hardware-Assisted Intrusion Detection by Preserving Reference Information Integrity.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

ECM: Effective Capacity Maximizer for high-performance compressed caching.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Sensitivity improvement in FSI CIS using the M1ToP™ smart process technique.
Proceedings of the International SoC Design Conference, 2012

A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Enhanced DHCP for the fast retrieval of the spectrum map for white space applications.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

White space backup network architecture for the connection continuity of wired and wireless access networks.
Proceedings of the MILCOM 2011, 2011

A semi-preemptive garbage collector for solid state drives.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

Inter-cell transmit power adaptation algorithm for coexistence of white space applications.
Proceedings of the 2011 IEEE Consumer Communications and Networking Conference, 2011

2010
Cross-Layer Dynamic Spectrum Map Management Framework for White Space Applications.
EURASIP J. Wirel. Commun. Netw., 2010

2009
Multimedia Mining on Manycore Architectures: The Case for GPUs.
Proceedings of the Advances in Visual Computing, 5th International Symposium, 2009

2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

2006
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Exploring Fault-Tolerant Network-on-Chip Architectures.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
A low latency router supporting adaptivity for on-chip interconnects.
Proceedings of the 42nd Design Automation Conference, 2005

Design and analysis of an NoC architecture from performance, reliability and energy perspective.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005


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