Jongkil Park

Orcid: 0000-0002-1302-3573

According to our database1, Jongkil Park authored at least 26 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2012
2014
2016
2018
2020
2022
2024
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
Implementation of two-step gradual reset scheme for enhancing state uniformity of 2D hBN-based memristors for image processing.
Neuromorph. Comput. Eng., 2024

A More Accurate Approximation of Activation Function with Few Spikes Neurons.
CoRR, 2024

High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics and Temporal Acceleration.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
Clock Offset Estimation for Systems With Asymmetric Packet Delays.
IEEE/ACM Trans. Netw., August, 2023

Unsupervised Spiking Neural Network with Dynamic Learning of Inhibitory Neurons.
Sensors, August, 2023

High Dynamic Range Digital Neuron Core With Time-Embedded Floating-Point Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Gradient Scaling on Deep Spiking Neural Networks with Spike-Dependent Local Information.
CoRR, 2023

Real-time Neural Connectivity Inference with Presynaptic Spike-driven Spike Timing-Dependent Plasticity.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023

2022
SPICE Study of STDP Characteristics in a Drift and Diffusive Memristor-Based Synapse for Neuromorphic Computing.
IEEE Access, 2022

2021
Spiking Neural Network (SNN) With Memristor Synapses Having Non-linear Weight Update.
Frontiers Comput. Neurosci., 2021

2020
Presynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017
Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.
IEEE Trans. Neural Networks Learn. Syst., 2017

Event-based delay-controlled stimulator controller with priority queue for real-time closed-loop neural interface system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link.
IEEE J. Solid State Circuits, 2016

2015
A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Large Scale Asynchronous Low-power VLSI Systems for Event- driven Sensory and Neural Processing.
PhD thesis, 2014

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link.
Proceedings of the Symposium on VLSI Circuits, 2014

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A 65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

A 12.6 mW 8.3 Mevents/s contrast detection 128×128 imager with 75 dB intra-scene DR asynchronous random-access digital readout.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Improved contrast sensitivity DVS and its application to event-driven stereo vision.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array.
Proceedings of the ESSCIRC 2013, 2013

2012
Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Event-driven neural integration and synchronicity in analog VLSI.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012


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