JongHyun Ko

According to our database, JongHyun Ko authored at least 7 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Vertical NAND flash memory-based matrix-matrix multiplication scheme for energy-efficient attention score computation.

JongHyun Ko, Sung-Ho Park, Jiseong Im, Jeonghyun Kim, Ryun-Han Koo, Yeongheon Yang, Jong-Ho Lee

Neurocomputing, 2025

2024

SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices.

JongHyun Ko, Dongseok Kwon, Joon Hwang, Kyu-Ho Lee, Seongbin Oh, Jeonghyun Kim, Jiseong Im, Ryun-Han Koo, Jae-Joon Kim, Jong-Ho Lee

Adv. Intell. Syst., April, 2024

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node.

Jaehoon Jeong, Yunjeong Shin, Hyundong Lee, JongHyun Ko, Jongbeom Kim, Taigon Song

IEEE Access, 2024

2023

T³L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure.

Jongbeom Kim, Hyundong Lee, JongHyun Ko, Bongjun Kim, Taigon Song

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design.

JongHyun Ko, Jongbeom Kim, TaeGam Jeong, Jaehoon Jeong, Taigon Song

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

2022

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node.

Jaehoon Jeong, JongHyun Ko, Taigon Song

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021

An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS.

JongHyun Ko, KwanWoo Park, Suhyeong Yong, TaeGam Jeong, Taehak Kim, Taigon Song

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021