Jongbeom Kim
Orcid: 0009-0005-4047-976X
According to our database1,
Jongbeom Kim
authored at least 11 papers
between 2020 and 2024.
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Bibliography
2024
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node.
IEEE Access, 2024
FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
T<sup>3</sup>L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 20th International SoC Design Conference, 2023
2022
Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
2020
IEEE Trans. Medical Imaging, 2020