Jong Wook Kwak
Orcid: 0000-0002-6639-3738
According to our database1,
Jong Wook Kwak
authored at least 40 papers
between 2004 and 2024.
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Bibliography
2024
PVS-GEN: Systematic Approach for Universal Synthetic Data Generation Involving Parameterization, Verification, and Segmentation.
Sensors, 2024
2023
Sensors, October, 2023
2022
PRIGM: Partial-Regression-Integrated Generic Model for Synthetic Benchmarks Robust to Sensor Characteristics.
IEICE Trans. Inf. Syst., 2022
2020
WPA: Write Pattern Aware Hybrid Disk Buffer Management for Improving Lifespan of NAND Flash Memory.
IEEE Trans. Consumer Electron., 2020
2018
Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory.
Microprocess. Microsystems, 2018
RbWL: Recency-Based Static Wear Leveling for Lifetime Extension and Overhead Reduction in NAND Flash Memory Systems.
IEICE Trans. Inf. Syst., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEICE Trans. Inf. Syst., 2017
2016
PBGC: Proxy Block-Based Garbage Collection for Index Structures in NAND Flash Memory.
IEICE Trans. Inf. Syst., 2016
HaWL: Hidden Cold Block-Aware Wear Leveling Using Bit-Set Threshold for NAND Flash Memory.
IEICE Trans. Inf. Syst., 2016
Migration Cost Sensitive Garbage Collection Technique for Non-Volatile Memory Systems.
IEICE Trans. Inf. Syst., 2016
2015
Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015
2014
IEICE Trans. Inf. Syst., 2014
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor.
IEICE Trans. Inf. Syst., 2014
Proceedings of the 2014 Conference on Research in Adaptive and Convergent Systems, 2014
2013
Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors.
IEICE Trans. Inf. Syst., 2013
Proceedings of the Research in Adaptive and Convergent Systems, 2013
2012
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors.
IEICE Trans. Inf. Syst., 2012
2010
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC).
Microprocess. Microsystems, 2010
J. Syst. Archit., 2010
Proceedings of the 43rd Hawaii International International Conference on Systems Science (HICSS-43 2010), 2010
2009
Performance Evaluation Model of Branch Input Vectors using Neural Network.
Proceedings of the 2009 International Conference on Computer Design, 2009
2008
High-performance embedded branch predictor by combining branch direction history and global branch history.
IET Comput. Digit. Tech., 2008
2007
Torus Ring: improving performance of interconnection network by modifying hierarchical ring.
Parallel Comput., 2007
Microprocess. Microsystems, 2007
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007
2006
J. Inf. Sci. Eng., 2006
J. Inf. Sci. Eng., 2006
Proceedings of the Computer and Information Sciences, 2006
History Length Adjustable <i>gshare</i> Predictor for High-Performance Embedded Processor.
Proceedings of the Computational Science and Its Applications, 2006
Proceedings of the Computational Science, 2006
2005
The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction.
IEICE Trans. Inf. Syst., 2005
Torus Ring: Improving Interconnection Network Performance by Modifying Hierarchical Ring.
IEICE Trans. Inf. Syst., 2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic.
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
2004
Ownership-Lacking Line First Policy of Remote Access Cache in NUMA System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004
Level 1 & Victim Cache Management with Processor Reuse Information.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004
A Novel Approach to Improve Cache Performance in Ring-Based Multiprocessors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004
Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor.
Proceedings of the Embedded and Ubiquitous Computing, 2004
Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.
Proceedings of the Embedded and Ubiquitous Computing, 2004