Jong Tae Kim
Orcid: 0000-0003-0290-0865
According to our database1,
Jong Tae Kim
authored at least 42 papers
between 1999 and 2024.
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Bibliography
2024
Interleaved Binary Demodulation Technique for Low-Cost and Fast-Response Visible Light Positioning Using Palindromic Sequences.
IEEE Internet Things J., January, 2024
2023
FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI.
Proceedings of the 20th International SoC Design Conference, 2023
2022
Sliding-Windowed Compensated Multiplexing for Nonstatic Targets in Tactile Sensor Arrays.
IEEE Trans. Ind. Electron., 2022
Efficient Error-Resilient Bus Coding Method Using Bit-Basis Orthogonal Integrative Multiplexing.
IEEE Trans. Emerg. Top. Comput., 2022
2020
High-Efficient and Low-Cost Biased Multilevel Modulation Technique for IM/DD-Based VLP Systems.
IEEE Access, 2020
2019
IEEE Access, 2019
VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick.
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International Conference on Information and Communication Technology Convergence, 2019
2018
Delay-Tolerant Multiplexed Stimulation and Its Processing Method for Multi-Channel Active Sensors.
IEEE Access, 2018
2017
Wirel. Pers. Commun., 2017
Sensors, 2017
A unified system level error model of crosstalk and electromigration for on-chip interconnect.
IEICE Electron. Express, 2017
2016
A pre-characterization method for multiple single-event transient analysis in cell-based designs.
Proceedings of the International SoC Design Conference, 2016
2015
Application of weighing matrices to simultaneous driving technique for capacitive touch sensors.
IEEE Trans. Consumer Electron., 2015
IEICE Electron. Express, 2015
Application of 4k-order Hadamard matrices to simultaneous driving capacitive touch systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
2014
STAM: System level state-machine-based thermal behavior analysis for multicore processor.
IEICE Electron. Express, 2014
IEICE Electron. Express, 2014
2011
A Study Using a Monte Carlo Method of the Optimal Configuration of a Distribution Network in Terms of Power Loss Sensing.
Sensors, 2011
Proceedings of the Information Security and Assurance - International Conference, 2011
2010
System Level Power Analysis for SoC Architecture Exploration.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010
2009
Microelectron. Reliab., 2009
Memory Error Analysis in Temporal TMR Viterbi Decoder.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009
Hardware Accelerator Design for Crank Angle Sensor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009
2008
IEICE Electron. Express, 2008
Proceedings of the 2nd International Conference on Ubiquitous Information Management and Communication, 2008
Radiation Pattern Reconstruction for Localization using Artificial Neural Network.
Proceedings of the 2008 International Conference on Artificial Intelligence, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Power Prediction of Application Software for Embedded System Based on PXA270 Processor.
Proceedings of the 2008 International Conference on Embedded Systems & Applications, 2008
2007
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007
Pipeline Scheduling with Dual Voltages for Low Power Design.
Proceedings of the 2007 International Conference on Computer Design, 2007
2006
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006
Equivalent Electric Circuit Modeling of Differential Structures in PCB with Genetic Algorithm.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006
Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006
VLSI Design of Multiple Specifications Viterbi Decoder.
Proceedings of the 2006 International Conference on Wireless Networks, 2006
2005
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
2004
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004
High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Universal Reed-Solomon Decoder Using Hardware/Software Co-Design Method.
Proceedings of the International Conference on VLSI, 2003
1999
VLSI Design, 1999