Jong-Pil Son
According to our database1,
Jong-Pil Son
authored at least 9 papers
between 2006 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2017
ACM Trans. Archit. Code Optim., 2017
2012
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.
IEICE Trans. Electron., 2011
2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2006
A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006