Jong Mun Park

According to our database1, Jong Mun Park authored at least 9 papers between 2003 and 2017.

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Bibliography

2017
Optical sensor process variability in a 0.18 μm high voltage CMOS technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2011
An analytical approach for physical modeling of hot-carrier induced degradation.
Microelectron. Reliab., 2011

2010
Interface traps density-of-states as a vital component for hot-carrier degradation modeling.
Microelectron. Reliab., 2010

2008
Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors.
IET Circuits Devices Syst., 2008

2007
Analysis of hot carrier effects in a 0.35 µm high voltage n-channel LDMOS transistor.
Microelectron. Reliab., 2007

2006
Evolution of a CMOS Based Lateral High Voltage Technology Concept.
Microelectron. J., 2006

2005
A method for generating structurally aligned grids for semiconductor device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
High-voltage lateral trench gate SOI-LDMOSFETs.
Microelectron. J., 2004

2003
Improving SiC lateral DMOSFET reliability under high field stress.
Microelectron. Reliab., 2003


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