Jong-Ho Kang
According to our database1,
Jong-Ho Kang
authored at least 7 papers
between 2012 and 2015.
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Bibliography
2015
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2012
A 1.2V 23nm 6F<sup>2</sup> 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012