Jong Duk Lee
According to our database1,
Jong Duk Lee
authored at least 13 papers
between 2003 and 2009.
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Bibliography
2009
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation.
IEICE Trans. Electron., 2009
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory.
IEICE Trans. Electron., 2009
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.
IEICE Trans. Electron., 2009
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design.
IEICE Trans. Electron., 2009
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).
IEICE Trans. Electron., 2009
2008
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.
IEICE Trans. Electron., 2008
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Trans. Electron., 2008
2007
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Trans. Electron., 2007
2004
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements.
Microelectron. Reliab., 2004
2003
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003