Jong-Chern Lee
According to our database1,
Jong-Chern Lee
authored at least 4 papers
between 2011 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
2011
2012
2013
2014
2015
2016
2017
0
1
2
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1
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
2016
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011