Jong-Chern Lee

According to our database, Jong-Chern Lee authored at least 4 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

High-Bandwidth Memory (HBM) Test Challenges and Solutions.

Hongshin Jun, Sang Kyun Nam, Han Ho Jin, Jong-Chern Lee, Yong Jae Park, Jaejin Lee

IEEE Des. Test, 2017

2016

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.

Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae-Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

High bandwidth memory(HBM) with TSV technique.

Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jaejin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee

Proceedings of the International SoC Design Conference, 2016

2011

A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM.

Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011