Jonathan Saul

According to our database, Jonathan Saul authored at least 11 papers between 1991 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2001

A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories.

Alistair A. McEwan, Jonathan Saul

J. Supercomput., 2001

1999

A High Speed Reconfigurable Firewall Based on Parameterization FPGA-Based Content Addressable Memories.

Alistair McEwan, Jonathan Saul, Andrew Bailey

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Hardware/Software Codesign for FPGA-based Systems.

Jonathan Saul

Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

1998

Re-synthesis in technology mapping for heterogeneous FPGAs.

Maurice Kilavuka Inuani, Jonathan Saul

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Technology mapping of heterogeneous LUT-based FPGAs.

Maurice Kilavuka Inuani, Jonathan Saul

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1996

Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form.

Nigel Lester, Jonathan Saul

Proceedings of the Field-Programmable Logic, 1996

1995

An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions.

Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

Architecture Oriented Logic Optimization for Lookup Table Based FPGAs.

Aiguo Lu, Jonathan Saul, Erik L. Dagless

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

An efficient verification algorithm for parallel controllers.

Krzysztof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna

Proceedings of the Proceedings EURO-DAC'94, 1994

1992

State Assignment Algorithms for Parallel Controller Synthesis.

James Pardey, Tomasz Kozlowski, Jonathan Saul, Martin Bolton

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations.

Jonathan Saul

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991