Jonathan E. Proesel

Orcid: 0000-0002-2507-1353

Affiliations:
  • IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
  • Nubis Communications, New Providence, NJ, USA


According to our database1, Jonathan E. Proesel authored at least 37 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023

2022


2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020

A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019


A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2017
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2017

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

2015
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
IEEE J. Solid State Circuits, 2015

A 25 Gb/s burst-mode receiver for low latency photonic switch networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Exploring the limits of high-speed receivers for multimode VCSEL-based optical links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

2013
35-Gb/s VCSEL-Based optical link using 32-nm SOI CMOS circuits.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

Optical receivers using DFE-IIR equalization.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links [Invited].
JOCN, 2012

25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs.
IEEE J. Solid State Circuits, 2011

Post-silicon calibration of analog CMOS using phase-change memory cells.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Statistical modeling and post manufacturing configuration for scaled analog CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Mismatch analysis and statistical design at 65 nm and below.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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