Jonathan Chang
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Bibliography
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the Information Security Practice and Experience, 2022
Reliability Analysis of Physically Unclonable Function by Using Aging Variability Simulation.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
2021
Computational Framework for the Identification of Neural Circuits Underlying Psychiatric Disorders.
PhD thesis, 2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021
A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Product Lifetime Estimation in 7nm with Large data of Failure Rate and Si-Based Thermal Coupling Model.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
2020
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology.
Sensors, 2019
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.
IEEE J. Solid State Circuits, 2019
FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems.
Integr., 2019
Learning Deep Parameterized Skills from Demonstration for Re-targetable Visuomotor Control.
CoRR, 2019
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Design-For-Reliability Flow in 7nm Products with Data Center and Automotive Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Learning representations of emotional speech with deep convolutional generative adversarial networks.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
2016
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions.
IEEE J. Solid State Circuits, 2015
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.
IEEE J. Solid State Circuits, 2015
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Product-level reliability estimator with budget-based reliability management in 20nm technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 31th International Conference on Machine Learning, 2014
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC<sup>2</sup>RA) circuitry achieving 3x reduction on speed variation for single ended arrays.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
Proceedings of the Fifth International Conference on Weblogs and Social Media, 2011
2010
Proceedings of the 2010 Workshop on Creating Speech and Language Data with Amazon's Mechanical Turk, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the Fourth International Conference on Weblogs and Social Media, 2010
Proceedings of the Haptics: Generating and Perceiving Tangible Sensations, 2010
2009
Comparison of child-human and child-computer interactions based on manual annotations.
Proceedings of the Second Workshop on Child, Computer and Interaction, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2007
IEEE J. Solid State Circuits, 2007
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.
IEEE J. Solid State Circuits, 2007
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development.
IEEE Comput. Archit. Lett., 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the Compiler Construction, 15th International Conference, 2006
2005
A 130-nm triple-V<sub>t</sub> 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.
IEEE J. Solid State Circuits, 2005
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005
2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996