Jonathan Borremans
According to our database1,
Jonathan Borremans
authored at least 37 papers
between 2006 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Sensors, 2018
An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2015
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015
2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Microelectron. Reliab., 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A Single-Inductor Dual-Band VCO in a 0.06mm<sup>2</sup> 5.6GHz Multi-Band Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006