Jonathan Beaumont

Orcid: 0000-0002-1217-8725

According to our database1, Jonathan Beaumont authored at least 19 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Scalable Autograding for Quantum Programming Assignments.
Proceedings of the 2024 on Innovation and Technology in Computer Science Education V. 1, 2024

2023
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.
ACM Trans. Parallel Comput., June, 2023

Event-based high throughput computing: A series of case studies on a massively parallel softcore machine.
IET Comput. Digit. Tech., January, 2023

2022
Event-driven DPD timings, temperature, power and migration data.
Dataset, May, 2022

2021
General hardware multicasting for fine-grained message-passing architectures.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020

Termination detection for fine-grained message-passing architectures.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing.
PhD thesis, 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Fine-Grained Management of Thread Blocks for Irregular Applications.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Regless: just-in-time operand staging for GPUs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Accelerating Smith-Waterman Alignment Workload with Scalable Vector Computing.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Plato: A Tool for Behavioural Specification of Asynchronous Circuits.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

2016
Mining Conditional Partial Order Graphs from Event Logs.
Trans. Petri Nets Other Model. Concurr., 2016

2015
WarpPool: sharing requests with inter-warp coalescing for throughput processors.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Compositional design of asynchronous circuits from behavioural concepts.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015


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