Jonas Doevenspeck
According to our database1,
Jonas Doevenspeck
authored at least 7 papers
between 2018 and 2024.
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Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the International Joint Conference on Neural Networks, 2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2019
Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications.
Proceedings of the 48th European Solid-State Device Research Conference, 2018