Jonas Diemer
According to our database1,
Jonas Diemer
authored at least 18 papers
between 2009 and 2017.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
2015
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers.
Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015
2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
2012
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012
Proceedings of the 14th International IEEE Symposium on High-Assurance Systems Engineering, 2012
2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Proceedings of the 11th International Conference on Embedded Software, 2011
2010
Proceedings of the NOCS 2010, 2010
A Polynomial-Time Algorithm for Computing Response Time Bounds in Static Priority Scheduling Employing Multi-linear Workload Bounds.
Proceedings of the 22nd Euromicro Conference on Real-Time Systems, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
A link arbitration scheme for quality of service in a latency-optimized network-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009