Jon T. Butler

IEICE Trans. Inf. Syst., 2024

2023

On Representation of Maximally Asymmetric Functions Based on Decision Diagrams.

[BibT_eX]

[DOI]

FLAP, 2023

On the distribution of sensitivities of symmetric Boolean functions.

[BibT_eX]

[DOI]

CoRR, 2023

Decomposition-Based Representation of Symmetric Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022

A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2022

On Decision Diagrams for Maximally Asymmetric Functions.

[BibT_eX]

[DOI]

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions.

[BibT_eX]

[DOI]

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

2021

Linear Decompositions for Multi-Valued Input Classification Functions.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

2020

On Optimum Linear Decomposition of Symmetric Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Properties of Multiple-Valued Partition Functions.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019

A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Maximally Asymmetric Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Realizing all Index Generation Functions by the Row-Shift Method.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018

An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions.

[BibT_eX]

[DOI]

FLAP, 2018

An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

An Exact Method to Enumerate Decomposition Charts for Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Decomposition of Index Generation Functions Using a Monte Carlo Method.

[BibT_eX]

[DOI]

Proceedings of the Advanced Logic Synthesis, 2018

2017

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016

A Parallel Approach in Computing Correlation Immunity up to Six Variables.

[BibT_eX]

[DOI]

Carole J. Etherington

Int. J. Found. Comput. Sci., 2016

Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A set partition number system.

[BibT_eX]

[DOI]

Australas. J Comb., 2016

An Efficient Heuristic for Linear Decomposition of Index Generation Functions.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

High-Speed Hardware Partition Generation.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014

Applications of Zero-Suppressed Decision Diagrams

[BibT_eX]

[DOI]

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79870-2, 2014

Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2014

EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2014

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2013

Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Hardware Index to Set Partition Converter.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Analysis of Multi-state Systems with Multi-state Components Using EVMDDs.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Hardware Index to Permutation Converter.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

A fast segmentation algorithm for piecewise polynomial numeric function generators.

[BibT_eX]

[DOI]

J. Comput. Appl. Math., 2011

Numeric Function Generators Using Piecewise Arithmetic Expressions.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Fast Hardware Computation of x Mod z.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Index to Constant Weight Codeword Converter.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

On the number of segments needed in a piecewise linear approximation.

[BibT_eX]

[DOI]

C. L. Frenzen

J. Comput. Appl. Math., 2010

Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Quaternary Decision Diagram Machine: Optimization of Its Code.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Enumeration of Bent Boolean Functions by Reconfigurable Computer.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

Progress in Applications of Boolean Functions

[BibT_eX]

[DOI]

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79812-2, 2009

A Quaternary Decision Diagram Machine and the Optimization of its Code.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

2008

Numerical function generators using bilinear interpolation.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Programmable Numerical Function Generators for Two-Variable Functions.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Numerical Function Generators Using LUT Cascades.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Implementation of Multiple-Valued CAM Functions by LUT Cascades.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Implementation of LPM Address Generators on FPGAs.

[BibT_eX]

[DOI]

Hui Qin

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

Average Path Length of Binary Decision Diagrams.

[BibT_eX]

[DOI]

Munehiro Matsuura

IEEE Trans. Computers, 2005

Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2005

Programmable Numerical Function Generators: Architectures and Synthesis Method.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

A fast method to derive minimum SOPs for decomposable functions.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002

Bi-Partition of Shared Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

Worst and Best Irredundant Sum-of-Products Expressions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

On the number of generators for transeunt triangles.

[BibT_eX]

[DOI]

Svetlana N. Yanushkevich

Vlad P. Shmerko

Discret. Appl. Math., 2001

On the minimization of SOPs for bi-decomposition functions.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions".

[BibT_eX]

[DOI]

Vlad P. Shmerko

Svetlana N. Yanushkevich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Experiments on FPRM Expressions for Partially Symmetric Logic Functions.

[BibT_eX]

[DOI]

Svetlana N. Yanushkevich

Vlad P. Shmerko

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1998

On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997

Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Planarity in ROMDD's of Multiple-Valued Symmetric Functions.

[BibT_eX]

[DOI]

J. L. Nowlin

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

Planar Multiple-Valued Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Multiple-Valued Logic Operations with Universal Literals.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Multiple-Valued Combinational Circuits with Feedback.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing.

[BibT_eX]

[DOI]

Cem Yildirim

Chyan Yang

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1992

On the Design of Cost-Tables for Realizing Multiple-Valued Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing.

[BibT_eX]

[DOI]

Parthasarathy P. Tirumalai

Robert C. Earle

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991.

[BibT_eX]

[DOI]

Susan W. Butler

Parthasarathy P. Tirumalai

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1991

The Design of Current Mode CMOS Multiple-Valued Circuits.

[BibT_eX]

[DOI]

Young-hoon Chang

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

Worst Case Number of Terms in Symmetric Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

1990

A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs.

[BibT_eX]

[DOI]

Joo-Kang Lee

IEEE Trans. Computers, 1990

On the Equivalence of Cost Functions in the Design of Circuits by Costtable.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays.

[BibT_eX]

[DOI]

John M. Yurchak

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach.

[BibT_eX]

[DOI]

Hans G. Kerkhoff

Siep Onneweer

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1989

On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions.

[BibT_eX]

[DOI]

Edward A. Bender

IEEE Trans. Computers, 1989

1988

Multiple-Valued CCD Circuits.

[BibT_eX]

[DOI]

Hans G. Kerkhoff

Computer, 1988

Multiple-Valued Logic - Guest Editor's Introduction.

[BibT_eX]

[DOI]

Computer, 1988

1985

Enumeration of Structured Flowcharts

[BibT_eX]

[DOI]

Edward A. Bender

J. ACM, July, 1985

1982

On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems.

[BibT_eX]

[DOI]

Inf. Sci., 1982

1981

Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1981

1980

Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs

[BibT_eX]

[DOI]

Patrick E. White

Inf. Control., September, 1980

1979

Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps

[BibT_eX]

[DOI]

Inf. Control., December, 1979

Decomposable Maps in General Tessellation Structures.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 1979

1978

Tandem Networks of Universal Cells.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

Asymptotic Aproximations for the Number of Fanout-Free Functions.

[BibT_eX]

[DOI]

Edward A. Bender

IEEE Trans. Computers, 1978

Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates.

[BibT_eX]

[DOI]

J. ACM, 1978

1976

Restricted Cellular Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1976

1975

On the Number of Functions Realized by Cascades and Disjunctive Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

1974

A Note on Cellular Automata Simulations

[BibT_eX]

[DOI]

Inf. Control., November, 1974

1973

Some Characteristics of Universal Cell Nets.

[BibT_eX]

[DOI]