Jon Garlett
According to our database1,
Jon Garlett
authored at least 5 papers
between 2003 and 2014.
Collaborative distances:
Collaborative distances:
Timeline
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2012
2014
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2003
In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003