Jon C. Muzio

Neil Anderson

VLSI Design, 2011

2007

A New Class of Cellular Automata.

[BibT_eX]

[DOI]

Hosna Jabbari

Lin Sun

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Analyzing Fault Models for Reversible Logic Circuits.

[BibT_eX]

[DOI]

Jing Zhong

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005

A Characterization of Antisymmetry in Boolean and Multi-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

Testing Methodologies for Embedded Systems and Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, First International Conference, 2004

An Investigation of Non-Linear Machines as PRPGs in BIST.

[BibT_eX]

Jing Zhong

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2002

Antisymmetries in the realization of Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Introducing redundant transformations for high level built-in self-testable synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

The IT Support for Acquired Brain Injury Patients - the Design and Evaluation of a New Software Package.

[BibT_eX]

[DOI]

Proceedings of the 35th Hawaii International Conference on System Sciences (HICSS-35 2002), 2002

Use of the Autocorrelation Function in the Classification of Switching Functions.

[BibT_eX]

[DOI]

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Redundant transformations for BIST testability metrics-based data path allocation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

An Integrated High-Level Test Synthesis for Built-in Self-Testable Designs.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000

Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

TOP: An Algorithm for Three-Level Optimization of PLDs.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

A Multimedia Virtual Lab for Digital Logic Design.

[BibT_eX]

[DOI]

E. Wang

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1997

Partial Symmetry in Cellular Automata Rule Vectors.

[BibT_eX]

[DOI]

Kevin Cattell

J. Electron. Test., 1997

Finding Composition Trees for Multiple-Valued Functions.

[BibT_eX]

[DOI]

Bernhard von Stengel

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping".

[BibT_eX]

[DOI]

Shujian Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Synthesis of one-dimensional linear hybrid cellular automata.

[BibT_eX]

[DOI]

Kevin Cattell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Analysis of One-Dimensional Linear Hybrid Cellular Automata over GF(q).

[BibT_eX]

[DOI]

Kevin Cattell

IEEE Trans. Computers, 1996

The dangers of simplistic delay models.

[BibT_eX]

[DOI]

J. Electron. Test., 1996

Testability of Generalized Multiple-Valued Reed-Muller Circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

Evaluating the safety of self-checking circuits.

[BibT_eX]

[DOI]

Shujian Zhang

J. Electron. Test., 1995

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

The Evaluation of Full Sensitivity for Test Generation in MVL Circuits.

[BibT_eX]

[DOI]

Dilian Gurov

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Analyzing and improving delay defect tolerance in pipelined combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits.

[BibT_eX]

[DOI]

Dilian Gurov

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

On the testability of array structures for FFT computation.

[BibT_eX]

[DOI]

Chao Feng

Fabrizio Lombardi

J. Electron. Test., 1993

Probabilistic Identification of Critical Components for Circuit Delays.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions.

[BibT_eX]

[DOI]

Patrick Kam Lui

IEEE Trans. Computers, 1992

Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

Constrained parity testing.

[BibT_eX]

[DOI]

Patrick Kam Lui

J. Electron. Test., 1991

1990

The analysis of one-dimensional linear cellular automata and their aliasing properties.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

On the testability of array structures for FFT computation.

[BibT_eX]

[DOI]

Fabrizio Lombardi

Yinan N. Shen

Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

Concerning the Maximum Size of the Terms in the Realization of Symmetric Functions.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1988

Space compaction for multiple-output circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987

Testing Programmable Logic Arrays by Sum of Syndromes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1987

1984

Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1984

1983

Spectral Fault Signatures for Internally Unate Combinational Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1983

1980

Composite Spectra and the Analysis of Switching Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

A class of two-place three-valued unary generators.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1980

1979

Classes of universal decision elements using negative substitutions.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1979

1978

A note concerning a sole sufficient operator.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1978

Generalized finite Post algebras.

[BibT_eX]

[DOI]

T. C. Wesselkamper

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1977

Three Cell Structures for Ternary Cellular Arrays.

[BibT_eX]

[DOI]

J. A. Bate

IEEE Trans. Computers, 1977

A prefix operator for a switching algebra.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1977

1976

A complete classification of three-place functors in two-valued logic.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1976

A ternary universal decision element.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1976

Concerning Completeness and Abelian Semigroups.

[BibT_eX]

[DOI]

Math. Log. Q., 1976

1974

Partial universal decision elements.

[BibT_eX]

[DOI]

Notre Dame J. Formal Log., 1974

1973

The cosubstitution condition.

[BibT_eX]

[DOI]