Johnson Tan
Orcid: 0000-0002-5459-9712
According to our database1,
Johnson Tan
authored at least 3 papers
between 2004 and 2020.
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Bibliography
2020
Proceedings of the 47th International Colloquium on Automata, Languages, and Programming, 2020
2005
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.
IEEE J. Solid State Circuits, 2005
2004
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004