Johnny Öberg
According to our database1,
Johnny Öberg
authored at least 57 papers
between 1994 and 2024.
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Bibliography
2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2022
AnoDe: A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA.
Proceedings of the 27th IEEE Pacific Rim International Symposium on Dependable Computing, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
2021
The VALU3S ECSEL project: Verification and validation of automated systems safety and security.
Microprocess. Microsystems, November, 2021
2019
Competence Networks in the Era of CPS - Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center.
Proceedings of the Cyber Physical Systems. Model-Based Design - 9th International Workshop, 2019
2018
Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems.
Microprocess. Microsystems, 2017
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Synthesis of VLIW Accelerators from Formal Descriptions in a Real-Time Multi-Core Environment.
Proceedings of the 14th FPGAworld Conference, 2017
2016
SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
A formal, model-driven design flow for system simulation and multi-core implementation.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015
Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
Going for Brain-Scale Integration - using FPGAs, TSVs and NOC based Artificial Neural Networks: A Case Study.
Proceedings of the FPGA World Conference 2014, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
An improved transmission scheme for error-prone inter-chip network-on-chip communication links implemented on FPGAs.
Proceedings of the 10th FPGAworld Conference, 2013
The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
2011
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011
2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2004
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.
Integr., 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
2003
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Control and communication performance analysis of embedded DSP systems in the MASIC methodology.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Des. Autom. Embed. Syst., 2000
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols.
Proceedings of the 1998 Design, 1998
1996
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
1994
Proceedings of the Proceedings EURO-DAC'94, 1994