John V. McCanny

According to our database, John V. McCanny authored at least 108 papers between 1985 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

New sensing technique for detecting application layer DDoS attacks targeting back-end database resources.

David Beckett, Sakir Sezer, John V. McCanny

Proceedings of the IEEE International Conference on Communications, 2017

2012

Design of interlock-free combined allocators for Networks-on-Chip.

Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers.

Lei Ma, Kevin Dickson, John McAllister, John V. McCanny

IEEE Trans. Signal Process., 2011

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip.

Ye Lu, John V. McCanny, Sakir Sezer

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

The Impact of Global Routing on the Performance of NoCs in FPGAs.

Ye Lu, John V. McCanny, Sakir Sezer

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems.

Ye Lu, John V. McCanny, Sakir Sezer

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

Evaluation of Random Delay Insertion against DPA on FPGAs.

Yingxi Lu, Máire O'Neill, John V. McCanny

ACM Trans. Reconfigurable Technol. Syst., 2010

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding.

Liang Lu, John V. McCanny, Sakir Sezer

IET Comput. Digit. Tech., 2010

High-Performance random data lookup for network processing.

Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Design and analysis of an advanced static blocked multithreading architecture.

Ye Lu, Sakir Sezer, John V. McCanny

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

TLM2.0 based timing accurate modeling method for complex NoC systems.

Ye Lu, Sakir Sezer, John V. McCanny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Advanced Multithreading Architecture with Hardware Based Scheduling.

Ye Lu, Sakir Sezer, John V. McCanny

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

Subpixel Interpolation Architecture for Multistandard Video Motion Estimation.

Liang Lu, John V. McCanny, Sakir Sezer

IEEE Trans. Circuits Syst. Video Technol., 2009

DDR3 based lookup circuit for high-performance network processing.

Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

NFA decomposition and multiprocessing architecture for parallel regular expression processing.

Yongping Liu, Sakir Sezer, John V. McCanny

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Is the differential frequency-based attack effective against random delay insertion?

Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008

From Bit Level Systolic Arrays to HDTV Processor Chips.

Roger F. Woods, John V. McCanny, John G. McWhirter

J. Signal Process. Syst., 2008

Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication.

Yen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha

J. Signal Process. Syst., 2008

High performance IP lookup circuit using DDR SDRAM.

Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Multi-standard sub-pixel interpolation architecture for video Motion Estimation.

Liang Lu, John V. McCanny, Sakir Sezer

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Reduced-complexity MSGR-based matrix inversion.

Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Differential Power Analysis of a SHACAL-2 hardware implementation.

Yingxi Lu, Máire O'Neill, John V. McCanny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Modified givens rotations and their application to matrix inversion.

Lei Ma, Kevin Dickson, John McAllister, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 2008

FPGA implementation and analysis of random delay insertion countermeasure against DPA.

Yingxi Lu, Máire O'Neill, John V. McCanny

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007

A versatile content addressable memory architecture.

Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns

Proceedings of the 2007 IEEE International SOC Conference, 2007

Reconfigurable video motion estimation processor.

Liang Lu, John V. McCanny, Sakir Sezer

Proceedings of the 2007 IEEE International SOC Conference, 2007

From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems.

John V. McCanny

Proceedings of the 15th International Conference on Digital Signal Processing, 2007

Exploring technology related design-space limitations of high performance network processing.

John V. McCanny, Sakir Sezer, Máire O'Neill

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression.

Liang Lu, John V. McCanny, Sakir Sezer

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Novel Content Addressable Memory Architecture for Adaptive Systems.

Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

Systolic Array Based Architecture for Variable Block-Size Motion Estimation.

Liang Lu, John V. McCanny, Sakir Sezer

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

WLAN security processor.

Neil Smyth, Máire McLoone, John V. McCanny

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$.

Ciaran McIvor, Máire McLoone, John V. McCanny

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An Adaptable And Scalable Asymmetric Cryptographic Processor.

Neil Smyth, Máire McLoone, John V. McCanny

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.

Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny

Proceedings of the Advanced International Conference on Telecommunications and International Conference on Internet and Web Applications and Services (AICT/ICIW 2006), 2006

2005

Application-specific instruction set processor for SoC implementation of modern signal processing algorithms.

Zhaohui Liu, Kevin Dickson, John V. McCanny

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Hardware Design of Sphere Decoding for MIMO Systems.

Zhaohui Liu, Kevin Dickson, John V. McCanny

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

High-Radix Systolic Modular Multiplication on Reconfigurable Hardware.

Ciaran McIvor, Máire McLoone, John V. McCanny

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

A VLSI architecture for variable block size video motion estimation.

Swee Yeow Yap, John V. McCanny

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Reusable silicon IP cores for discrete wavelet transform applications.

Shahid Masud, John V. McCanny

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p).

Ciaran McIvor, Máire McLoone, John V. McCanny

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication.

Máire McLoone, Ciaran McIvor, John V. McCanny

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

FPGA Montgomery Multiplier Architectures - A Comparison.

Ciaran McIvor, Máire McLoone, John V. McCanny

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

Rijndael FPGA Implementations Utilising Look-Up Tables.

Máire McLoone, John V. McCanny

J. VLSI Signal Process., 2003

Generic SoC QR array processor for adaptive beamforming.

Zhaohui Liu, John V. McCanny, Gaye Lightbody, Richard L. Walke

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A high-speed, low latency RSA decryption silicon core.

Ciaran McIvor, Máire McLoone, John V. McCanny

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Implementation of adaptive beamforming based on QR decomposition for CDMA.

Zhaohui Liu, John V. McCanny

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Very High Speed 17 Gbps SHACAL Encryption Architecture.

Máire McLoone, John V. McCanny

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A VLSI Architecture for Advanced Video Coding Motion Estimation.

Swee Yeow Yap, John V. McCanny

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

A floating-point CORDIC based SVD processor.

Zhaohui Liu, Kevin Dickson, John V. McCanny

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

A mixed cost-function adaptive algorithm for ADSL time-domain equalization.

Kok Sing Yap, John V. McCanny

Proceedings of the IEEE International Conference on Communications, 2002

A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems.

Kok Sing Yap, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 2002

Design and implementation of the symmetrically extended 2-D Wavelet Transform.

Paul V. McCanny, Shahid Masud, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 2002

Efficient single-chip implementation of SHA-384 and SHA-512.

Máire McLoone, John V. McCanny

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform.

Paul V. McCanny, John V. McCanny, Shahid Masud

Proceedings of the 11th European Signal Processing Conference, 2002

2001

Design of Silicon IP Cores for Biorthogonal Wavelet Transforms.

Shahid Masud, John V. McCanny

J. VLSI Signal Process., 2001

An efficient architecture for the 2-D biorthogonal discrete wavelet transform.

Paul V. McCanny, Shahid Masud, John V. McCanny

Proceedings of the 2001 International Conference on Image Processing, 2001

Generic scheduling methods for a linear QR array SoC processor.

Zhaohui Liu, Gaye Lightbody, Richard L. Walke, Yi Hu, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 2001

Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.

Máire McLoone, John V. McCanny

Proceedings of the Field-Programmable Logic and Applications, 2001

High Performance Single-Chip FPGA Rijndael Algorithm Implementations.

Máire McLoone, John V. McCanny

Proceedings of the Cryptographic Hardware and Embedded Systems, 2001

2000

Linear QR Architecture for a Single Chip Adaptive Beamformer.

Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny

J. VLSI Signal Process., 2000

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors.

Robert Hamill, John V. McCanny, Richard L. Walke

IEEE Trans. Signal Process., 2000

Wavelet packet transforms for system-on-chip applications.

Shahid Masud, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 2000

1999

Rapid design of application specific FFT cores.

Tiong Jiu Ding, John V. McCanny, Yunsheng Hu

IEEE Trans. Signal Process., 1999

Rapid design of discrete orthonormal wavelet transforms using silicon IP components.

Shahid Masud, John V. McCanny

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Novel mapping of a linear QR architecture.

Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998

Rapid Design of Discrete Orthonormal Wavelet Transforms.

Shahid Masud, John V. McCanny

Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

Finding a suitable wavelet for image compression applications.

Shahid Masud, John Vincent McCanny

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Discrete cosine transform generator for VLSI synthesis.

Jill K. Hunter, John V. McCanny

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Rapid design of discrete transform cores.

Jill K. Hunter, John V. McCanny

Proceedings of the 9th European Signal Processing Conference, 1998

1997

Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS".

David W. Trainor, Roger F. Woods, John V. McCanny

J. VLSI Signal Process., 1997

Hierarchical VHDL libraries for DSP ASIC design.

John V. McCanny, Douglas Ridge, Yi Hu, Jill K. Hunter

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996

A 64-point Fourier transform chip for video motion compensation using phase correlation.

Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods

IEEE J. Solid State Circuits, 1996

Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel.

B. D. E. Smith, John V. McCanny

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Error analysis of FFT architectures for digital video applications.

Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation.

Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995

VLSI architectures for vector quantization.

M. Yan, John V. McCanny, Yi Hu

J. VLSI Signal Process., 1995

A Systematic Methodology for the Design of High Performance Recursive Digital Filters.

Stephen E. McQuillan, John V. McCanny

IEEE Trans. Computers, 1995

1994

Fast VLSI algorithms for division and square root.

Stephen E. McQuillan, John V. McCanny

J. VLSI Signal Process., 1994

Automated design of DSP array processor chips.

John V. McCanny, Yi Hu, M. Yan

Proceedings of the International Conference on Application Specific Array Processors, 1994

1993

New algorithms and VLSI architectures for SRT division and square root.

Stephen E. McQuillan, John V. McCanny, Robert Hamill

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992

Systolic inner product arrays with automatic word rounding.

M. Yan, John V. McCanny

J. VLSI Signal Process., 1992

High performance VLSI architecture for Wave Digital Filtering.

Rajinder Jit Singh, John V. McCanny

J. VLSI Signal Process., 1992

The systematic design of high performance digital filters.

B. P. McGovern, Roger F. Woods, John V. McCanny

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Algorithms and architectures for high performance recursive filtering.

Stephen E. McQuillan, John V. McCanny

Proceedings of the Application Specific Array Processors, 1992

1991

Design of a Highly Pipelined 2nd Order IIR Filter Chip.

O. C. McNally, John V. McCanny, Roger F. Woods

Proceedings of the VLSI 91, 1991

A VLSI architecture for multiplication, division and square root.

Stephen E. McQuillan, John V. McCanny

Proceedings of the 1991 International Conference on Acoustics, 1991

Design and test of a bit parallel 2nd order IIR filter structure.

O. C. McNally, William P. Marnane, John V. McCanny

Proceedings of the 1991 International Conference on Acoustics, 1991

On the use of most significant digit first arithmetic in the design of high performance DSP chips.

John V. McCanny

Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

A wave digital filter three-port adaptor with fine grained pipelining.

Rajinder Jit Singh, John V. McCanny

Proceedings of the Application Specific Array Processors, 1991

A 40 megasample IIR filter chip.

O. C. McNally, John V. McCanny, Roger F. Woods

Proceedings of the Application Specific Array Processors, 1991

1990

A bit-level systolic architecture for implementing a VQ tree search.

M. Yan, John V. McCanny

J. VLSI Signal Process., 1990

The use of data dependence graphs in the design of bit-level systolic arrays.

John V. McCanny, John G. McWhirter, Sun-Yuan Kung

IEEE Trans. Acoust. Speech Signal Process., 1990

Optimized bit level architectures for IIR filtering.

O. C. McNally, John V. McCanny, Roger F. Woods

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

VLSI architectures for digital image coding.

M. Yan, John V. McCanny, Yi Hu

Proceedings of the 1990 International Conference on Acoustics, 1990

Pipelined two-port adaptor for wave digital filtering.

Rajinder Jit Singh, John V. McCanny, Roger F. Woods

Proceedings of the 1990 International Conference on Acoustics, 1990

Systolic two-port adaptor for high performance wave digital filtering.

Rajinder Jit Singh, John V. McCanny

Proceedings of the Application Specific Array Processors, 1990

Systolic VLSI compiler (SVC) for high performance vector quantisation chips.

Y. Hu, John V. McCanny, M. Yan

Proceedings of the Application Specific Array Processors, 1990

1989

Bit-Level systolic architectures for high performance IIR filtering.

Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny

J. VLSI Signal Process., 1989

A bit-level systolic architecture for very high performance IIR filters.

Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 1989

1988

Systolic IIR filters with bit level pipelining.

Roger F. Woods, Simon C. Knowles, John V. McCanny, John G. McWhirter

Proceedings of the IEEE International Conference on Acoustics, 1988

An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation.

S. M. F. Smyth, John V. McCanny, P. Challener

Proceedings of the IEEE International Conference on Acoustics, 1988

An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation using music signals.

S. M. F. Smyth, John V. McCanny, P. Challener

Proceedings of the IEEE International Conference on Acoustics, 1988

1987

Some Systolic Array Developments in the United Kingdom.

John V. McCanny, John G. McWhirter

Computer, 1987

Transformed sub-band coding of speech using vector quantization.

H. A. Kaouri, John V. McCanny

Proceedings of the European Conference on Speech Technology, 1987

1986

A high speed CMOS/SOS implementation of a bit level systolic correlator.

J. C. White, John V. McCanny, A. McCabe, John G. McWhirter, R. Evans

Proceedings of the IEEE International Conference on Acoustics, 1986

Mapping system level functions on to bit level systolic arrays.

John V. McCanny

Proceedings of the IEEE International Conference on Acoustics, 1986

1985

A systolic implementation of the Winograd Fourier transform algorithm.

J. S. Ward, John V. McCanny, John G. McWhirter

Proceedings of the IEEE International Conference on Acoustics, 1985