John V. Arthur
According to our database1,
John V. Arthur
authored at least 36 papers
between 2005 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2019
Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Inference.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019
2018
Low Precision Policy Distillation with Application to Low-Power, Real-time Sensation-Cognition-Action Loop with Neuromorphic Computing.
CoRR, 2018
Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Embedded Inference.
CoRR, 2018
2017
Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor.
IEEE Trans. Computers, 2017
2016
IEEE Trans. Biomed. Circuits Syst., 2016
Proc. Natl. Acad. Sci. USA, 2016
Deep neural networks are robust to weight binarization and other non-linear distortions.
CoRR, 2016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations.
Proc. IEEE, 2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the Advances in Neural Information Processing Systems 20, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the Advances in Neural Information Processing Systems 18 [Neural Information Processing Systems, 2005