John Sartori

Orcid: 0000-0002-3467-9862

According to our database1, John Sartori authored at least 50 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Solar Textiles for Off-grid Populations in Sub-Saharan Africa.
Proceedings of the 2022 ACM International Symposium on Wearable Computers, 2022

Towards Fairness and Interpretability: Clinical Decision Support for Acute Coronary Syndrome.
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022

A scalable symbolic simulation tool for low power embedded systems.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
NLP Methods for Extraction of Symptoms from Unstructured Data for Use in Prognostic COVID-19 Analytic Models.
J. Artif. Intell. Res., 2021

Designing a Cost-Effective Cache Replacement Policy using Machine Learning.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Property-driven Automatic Generation of Reduced-ISA Hardware.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2019
DImplementing First-order Optimization Methods: Algorithmic Considerations and Bespoke Microcontrollers.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints.
IEEE Micro, 2018

Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems.
ACM Comput. Surv., 2018

Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors.
ACM Trans. Comput. Syst., 2017

Ultra-Low-Power Processors.
IEEE Micro, 2017

Software-based gate-level information flow security for IoT systems.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Scalable N-worst algorithms for dynamic timing and activity analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Enabling Effective Module-Oblivious Power Gating for Embedded Processors.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Approximate compression: enhancing compressibility through data approximation.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

2016
Automated Algorithmic Error Resilience Based on Outlier Detection.
IEEE Micro, 2016

Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Automated error prediction for approximate sequential circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
GPU-Accelerated Nick Local Image Thresholding Algorithm.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Software canaries: software-based path delay fault testing for variation-aware energy-efficient design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Automated Algorithmic Error Resilience for Structured Grid Problems Based on Outlier Detection.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Enhancing the Efficiency of Energy-Constrained DVFS Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Branch and Data Herding: Reducing Control and Memory Divergence for Error-Tolerant GPU Applications.
IEEE Trans. Multim., 2013

Exploiting Timing Error Resilience in Processor Architecture.
ACM Trans. Embed. Comput. Syst., 2013

High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity.
IEEE Comput. Archit. Lett., 2013

Low-power, low-storage-overhead chipkill correct via multi-line error correction.
Proceedings of the International Conference for High Performance Computing, 2013

Statistical analysis and modeling for error composition in approximate computation circuits.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Programmable stochastic processors
PhD thesis, 2012

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Power balanced pipelines.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

On software design for stochastic processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Compiling for energy efficiency on timing speculative processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Stochastic Computing.
Found. Trends Electron. Des. Autom., 2011

On the efficacy of NBTI mitigation techniques.
Proceedings of the Design, Automation and Test in Europe, 2011

Stochastic computing: embracing errors in architectureand design of processors and applications.
Proceedings of the 14th International Conference on Compilers, 2011

Architecting processors to allow voltage/reliability tradeoffs.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Variation-aware speed binning of multi-core processors.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Optimal power/performance pipelining for error resilient processors.
Proceedings of the 28th International Conference on Computer Design, 2010

Designing a processor from the ground up to allow voltage/reliability tradeoffs.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Low-Overhead, High-Speed Multi-core Barrier Synchronization.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Overscaling-friendly timing speculation architectures.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Scalable stochastic processors.
Proceedings of the Design, Automation and Test in Europe, 2010

Recovery-driven design: a power minimization methodology for error-tolerant processor modules.
Proceedings of the 47th Design Automation Conference, 2010

Slack redistribution for graceful degradation under voltage overscaling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Three scalable approaches to improving many-core throughput for a given peak power budget.
Proceedings of the 16th International Conference on High Performance Computing, 2009

Distributed peak power management for many-core architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Servo: a programming model for many-core computing.
SIGARCH Comput. Archit. News, 2008


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