John Reuben

According to our database, John Reuben authored at least 17 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory.

John Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2023

Hyper Dimensional Computing with Ferroelectric Tunneling Junctions.

Stefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories.

John Reuben, Dietmar Fey, Stefan Slesazeck

Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2022

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic.

Vijaya Lakshmi, John Reuben, Vikramkumar Pudi

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Inner Product Computation In-Memory Using Distributed Arithmetic.

Vijaya Lakshmi, Vikramkumar Pudi, John Reuben

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.

John Reuben, Stefan Pechmann

IEEE Trans. Very Large Scale Integr. Syst., 2021

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles.

John Reuben, Dietmar Fey

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic.

Dietmar Fey, John Reuben, Stefan Slesazeck

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Direct state transfer in MLC based memristive ReRAM devices for ternary computing.

Dietmar Fey, John Reuben

Proceedings of the European Conference on Circuit Theory and Design, 2020

A Parallel-friendly Majority Gate to Accelerate In-memory Computation.

John Reuben, Stefan Pechmann

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM.

John Reuben, Dietmar Fey

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

A Taxonomy and Evaluation Framework for Memristive Logic.

John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky

Proceedings of the Handbook of Memristor Networks., 2019

2017

Memristive logic: A framework for evaluation and comparison.

John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.

Kamineni Sumanth Kumar, John Reuben

J. Circuits Syst. Comput., 2016

2014

Low Power fractional-n frequency Divider with Improved Resolution.

V. Mohammed Zackriya, John Reuben, Ashim Harsh, Harish M. Kittur

J. Circuits Syst. Comput., 2014

A novel clock generation algorithm for system-on-chip based on least common multiple.

John Reuben, Harish M. Kittur, Mohd Shoaib

Comput. Electr. Eng., 2014

2013

Capacitance driven clock mesh synthesis to minimize skew and power dissipation.

John Reuben, V. Mohammed Zackriya, Salma Nashit, Harish M. Kittur

IEICE Electron. Express, 2013