John Paul Strachan
Orcid: 0000-0002-1382-3677
According to our database1,
John Paul Strachan
authored at least 50 papers
between 2010 and 2024.
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Bibliography
2024
An Analytical Method to Induce a Multistable Periodic Response to Pulse Trains in a ReRAM Cell.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024
Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
Computer, March, 2023
High-Speed and Energy-Efficient Non-Volatile Silicon Photonic Memory Based on Heterogeneously Integrated Memresonator.
CoRR, 2023
Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Analog Feedback-Controlled Memristor Programming Circuit for Analog Content Addressable Memory.
Proceedings of the IEEE International Conference on Metrology for eXtended Reality, 2023
Local Fading Memory Effects in a Tantalum Oxide ReRAM Cell from Hewlett Packard Labs.
Proceedings of the IEEE International Conference on Metrology for eXtended Reality, 2023
State-Space Modeling and Tuning of Memristors for Neuromorphic Computing Applications.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
2022
Neuromorph. Comput. Eng., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
CoRR, 2021
Defect tolerant in-memory analog computing with CMOS-integrated nanoscale crossbars: Invited.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.
IEEE Trans. Computers, 2020
Classical Adiabatic Annealing in Memristor Hopfield Neural Networks for Combinatorial Optimization.
Proceedings of the International Conference on Rebooting Computing, 2020
2019
Nat. Mach. Intell., 2019
Nat. Mach. Intell., 2019
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR, 2019
FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator.
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
IEEE Micro, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018
2017
Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.
IEEE Consumer Electron. Mag., 2017
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010