John P. Uehlin
Orcid: 0000-0001-7443-6884
According to our database1,
John P. Uehlin
authored at least 4 papers
between 2016 and 2020.
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Bibliography
2020
A 0.0023 mm<sup>2</sup>/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression.
IEEE Trans. Biomed. Circuits Syst., 2020
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS.
IEEE J. Solid State Circuits, 2020
2019
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2016
A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016