John P. Knight

According to our database1, John P. Knight authored at least 14 papers between 1985 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2005
Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
Physical Resource Binding for a Coarse Grain Reconfigurable Array.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2002
Compatible cell connections for multifamily dynamic logic gates.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2001

1996
Optimizing Power in ASIC Behavioral Synthesis.
IEEE Des. Test Comput., 1996

1995
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level.
Proceedings of the 32st Conference on Design Automation, 1995

1993
Operations research in the high-level synthesis of integrated circuits.
Comput. Oper. Res., 1993

Genetic Algorithms for the Optimization of Integrated Circuits Synthesis.
Proceedings of the 5th International Conference on Genetic Algorithms, 1993

1989
Force-directed scheduling for the behavioral synthesis of ASICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Algorithms for high-level synthesis.
IEEE Des. Test, 1989

Scheduling and Binding Algorithms for High-Level Synthesis.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987
Force-Directed Scheduling in Automatic Data Path Synthesis.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
HAL: a multi-paradigm approach to automatic data path synthesis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985


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